Success Drives PanasonicSoC Adoption of IC Compiler II Highlights · IC Compiler II enables first-time working silicon for high-performance multimedia design in 40-nm technology · 5X faster design implementation enables faster turn-around-time for
Synopsys Synplify Pro Synthesis Tool Delivers Superior Quality of Results for Users of Gowin Semiconductor FPGAs Highlights: Multi-year agreement provides Gowin FPGA users with Synopsys’ Synplify Pro high-quality FPGA synthesis tool to
Highlights: DFTMAX™ Ultra compression technology deliver 11X higher compression and reduced test time Higher test quality with shorter test time drove VIA’s standardization on DFTMAX Ultra for pin-limited designs Deployment of DFTMAX
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, will showcase advances in its comprehensive synthesis-based test solution during the International
Achieves Single-pass Timing and Power ECO Closure on Multiple Tapeouts Including FinFET Highlights HiSilicon has chosen PrimeTime ADV for timing closure in advanced IC design flow Accurate single-pass timing and power closure
Highlights: TSMC selects Synopsys as its “Partner of the Year” for interface IP and tool enablement for the 5th consecutive year The Interface IP Partner of the Year award selection criteria include
Native SystemVerilog-based VIP for PCI Express architecture now supports M-PCIe technology, with built-in coverage, verification plan and protocol-aware debug Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used
Power Savings Enabled by Unique Techniques and Design Flow Supported by Design Compiler Graphical, IC Compiler and PrimeTime Tools Highlights: • MB86S70 processor designed with ARM®MaliTM-T624 GPUs, ARM Cortex®-A15 and Cortex-A7 processors
Single, unified Liberty variation format standardized by the IEEE Industry Standards Board Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic
Industry Leaders Sign Multi-year Subscription Agreement to Accelerate Design and Verification of ARM-based SoCs using Synopsys Tools Highlights: Extended collaboration to benefit mutual customers with optimized Synopsys implementation, verification and software development
Certification of Digital and Custom Tools Enables Early Adopters to Realize QoR Benefits of the New Processes Highlights: Digital and custom tools from Galaxy™ Design Platform are ready for TSMC10-nm FinFET and 16-nm FinFET+ processes Successful 10-nm
Next-Generation Verification Platform to Accelerate Time-to-Market by Months Highlights: *Increasing System-on-Chip (SoC) complexity and software content combined with rising time-to-market pressures are driving the need for a next-generation verification solution that spans
